LTC4215/LTC4215-2
21
4215fe
APPLICATIONS INFORMATION
Alert Response Protocol
When any of the fault bits in FAULT register D are set, an
optional bus alert is generated if the appropriate bit in
the ALERT register B is also set. If an alert is enabled, the
corresponding fault causes the ALERT pin to pull low. After
the bus master controller broadcasts the Alert Response
Address, the LTC4215 responds with its address on the
SDA line and then release ALERT as shown in Figure 11.
The ALERT line is also released if the device is addressed
by the bus master. The ALERT signal is not pulled low
again until the FAULT register indicates a different fault
has occurred or the original fault is cleared and it occurs
again. Note that this means repeated or continuing faults
do not generate alerts until the associated FAULT register
bit has been cleared.
Table 1A. LTC4215 Device Addressing (UH24 Package)
DESCRIPTION
DEVICE
ADDRESS
DEVICE ADDRESS
LTC4215UH
ADDRESS PINS
h
7
6
5
4
3
2
1
0
ADR2
ADR1
ADR0
Mass Write
BE
1
0
1
1
1
1
1
0
X
X
X
Alert Response
19
0
0
0
1
1
0
0
1
X
X
X
0
80
1
0
0
0
0
0
0
X
L
NC
L
1
82
1
0
0
0
0
0
1
X
L
H
NC
2
84
1
0
0
0
0
1
0
X
L
NC
NC
3
86
1
0
0
0
0
1
1
X
L
NC
H
4
88
1
0
0
0
1
0
0
X
L
L
L
5
8A
1
0
0
0
1
0
1
X
L
H
H
6
8C
1
0
0
0
1
1
0
X
L
L
NC
7
8E
1
0
0
0
1
1
1
X
L
L
H
8
90
1
0
0
1
0
0
0
X
NC
NC
L
9
92
1
0
0
1
0
0
1
X
NC
H
NC
10
94
1
0
0
1
0
1
0
X
NC
NC
NC
11
96
1
0
0
1
0
1
1
X
NC
NC
H
12
98
1
0
0
1
1
0
0
X
NC
L
L
13
9A
1
0
0
1
1
0
1
X
NC
H
H
14
9C
1
0
0
1
1
1
0
X
NC
L
NC
15
9E
1
0
0
1
1
1
1
X
NC
L
H
16
A0
1
0
1
0
0
0
0
X
H
NC
L
17
A2
1
0
1
0
0
0
1
X
H
H
NC
18
A4
1
0
1
0
0
1
0
X
H
NC
NC
19
A6
1
0
1
0
0
1
1
X
H
NC
H
20
A8
1
0
1
0
1
0
0
X
H
L
L
21
AA
1
0
1
0
1
0
1
X
H
H
H
22
AC
1
0
1
0
1
1
0
X
H
L
NC
23
AE
1
0
1
0
1
1
1
X
H
L
H
24
B0
1
0
1
1
0
0
0
X
L
H
L
25
B2
1
0
1
1
0
0
1
X
NC
H
L
26
B4
1
0
1
1
0
1
0
X
H
H
L
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